Configuration bits For PIC18F4550

Configuration bits are special bits used for controlling different features in the Microcontroller. These are read during startup/reset and enable or disable different hardware features based on the values of bits. Using these bits, we can essentially control where is the clock source, do the application needs watchdog timer etc. They can only be modified during programming time. They can be programmed to select various device configurations. These bits are mapped starting at program memory location 300000h.

Configuration bits are not accessible to the user through code because it belongs to the configuration memory space, not the user program memory space. So it can only be accessed using table reads and table writes.

Configuration bits are directives written in the software. MPLAB X IDE has a configuration bits window to generate the directives based on the selected options. The generated configuration bits can be used in the application by directly copying and pasting or saving it as a separate file and including it in the project.

Registers used for the setup of Configuration bits in PIC18F4550

PIC18F4550 has 14 configuration registers, CONFIG1L, CONFIG1H, CONFIG2L, CONFIG2H, CONFIG3H, CONFIG4L, CONFIG5L, CONFIG5H, CONFIG6L, CONFIG6H, CONFIG7L, CONFIG7H, DEVID1, and DEVID2. The last two are device ID registers which are read-only. Other 12 registers are used for setting configuration bits for PIC18F4550.

Bitwise description of each configuration register is given in PIC18F4550 datasheet, section 25. The configuration settings for PIC18F devices can also be referred.

Defining configuration bits in XC8

We use the following format to define configuration bits. To set configuration bits, use the pragma directives.

#pragma config CONFIG_BIT_NAME = CONFIG_VALUE

For example, to set oscillator source as external HS oscillator.

#pragma config FOSC = HS        // Oscillator Selection bits (HS oscillator (HS))

Oscillator configurations

PIC18F4550 can be operated in 12 different oscillator modes. We can choose the mode based on the project requirement. Microchip developer has an extensive tutorial on different oscillator options. Below table lists different options.

Oscillator configuration bits - PIC18F4550 — Oscillator configuration bits – PIC18F4550

Fail-safe clock monitor

The fail-safe monitor allows the device to switch over to internal oscillators when external clock fails. This option can be enabled by setting the FCMEM configuration bit.

#pragma config FCMEM = OFF       // Failsafe Disabled

#pragma config FCMEM = ON       // Failsafe enabled

Internal/External switch over

Using this configuration bit, we can enable clock switcher between internal and external clocks.

#pragma config IESO = OFF       // Switch over Disabled, Put IESO = ON to enable

USB clock selection

This will select Full-Speed USB Clock Source, there are two choices. One from OSC1/OSC2 or from 96MHz PLL/2. USB accepts only 48MHz (full speed) and 6MHz (low speed) frequency clocks. If the clock is 6 MHz or 48 MHz, it can be used directly. Otherwise, we need to use PLL and postscaler to process the clock.

#pragma config USBDIV = 1       // Clock source from OSC1/OSC2

#pragma config USBDIV = 2       // Clock source from 96MHz PLL/2

96MHz PLL prescaler

PLL is used for generating a clock for USB. It multiplies the input by 24. The prescaler processes the clock before inputting to the PLL. For using this option, first set the configuration bit for clock selection as HSPLL.
The PLL prescaler divides the clock to get the 4MHz input to the PLL. The value depends on the oscillator. For 20MHz oscillator, it is 4.

#pragma config PLLDIV = 1       // No divide (4MHz input)
#pragma config PLLDIV = 2       // Divide by 2 (8MHz input)
#pragma config PLLDIV = 3       // Divide by 3 (12MHz input)
#pragma config PLLDIV = 4       // Divide by 4 (16MHz input)
#pragma config PLLDIV = 5       // Divide by 5 (20MHz input)
#pragma config PLLDIV = 6       // Divide by 6 (24MHz input)
#pragma config PLLDIV = 10      // Divide by 10 (40MHz input)
#pragma config PLLDIV = 12      // Divide by 12 (48MHz input)

CPU System Clock Postscaler

System clock postscaler is used for scaling the frequency before delivering to the clock. For example, it is useful to generate 48MHz from the PLL by using OSC1_PLL2 option.

#pragma config CPUDIV = OSC1_PLL2       // [OSC1/OSC2 Src: /1][96MHz PLL Src: /2]

#pragma config CPUDIV = OSC2_PLL3       // [OSC1/OSC2 Src: /2][96MHz PLL Src: /3]

#pragma config CPUDIV = OSC3_PLL4       // [OSC1/OSC2 Src: /3][96MHz PLL Src: /4]

#pragma config CPUDIV = OSC4_PLL6       // [OSC1/OSC2 Src: /4][96MHz PLL Src: /6]

Power up timer

The power-up timer introduces a small delay after power-up reset or brown-out reset. These settings can be controlled by below options.

#pragma config PWRT = ON       // Power up timer enabled

#pragma config PWRT = OFF       // Power up timer Disabled

Brown out reset

Brown out reset allows the microcontroller to reset when the supply voltage drops below a specific voltage. The voltage can be specified by Brown out voltage configuration settings. There are four options as listed below. There is also an option to control the reset via software.

<br>#pragma config BOR = OFF        // Brown out reset disabled<br><br>#pragma config BOR = SOFT       // Brown out reset controlled by SBOREN<br><br>#pragma config BOR = ON_ACTIVE  // Enabled when the device is not in SLEEP, SBOREN bit is disabled<br><br>#pragma config BOR = ON         // Brown out reset enabled, SBOREN bit is disabled

Brown out voltage

Using this configuration bit, we can set the voltage for brownout reset.

#pragma config BORV = 46        // Brown out voltage = 4.6V

#pragma config BORV = 43        // Brown out voltage = 4.3V

#pragma config BORV = 28        // Brown out voltage = 2.8V

#pragma config BORV = 21        // Brown out voltage = 2.1V

USB voltage regulator enable

VREGEN is for enabling or disabling internal USB voltage regulator. If you are feeding the USB voltage regulator externally, then disable it by setting VREGEN to zero.

#pragma config VREGEN = OFF       // USB voltage regulator disabled

#pragma config VREGEN = ON       // USB voltage regulator enabled

Watchdog timer

Watchdog timer detects when the microcontroller is stuck in endless loop. So we can set the timer a value, and if the execution time is exceeded by the value the reset happens.

#pragma config WDT = OFF       // HW Disabled - SW Controlled

#pragma config WDT = ON       // HW Enabled - SW Disabled

Watchdog prescaler

The watchdog timer period can be multiplied and is set by the WDTPS bit. Effectively, the period can be set from 4ms to 131.072 seconds. From the values 1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384 and 32768, select the appropriate prescaler value.

#pragma config WDTPS = 128       // 1:128 prescalar selected

MCLR Enable

MCLR pin provides a method for triggering external reset. The reset can be generated by holding the pin low. MCLR can be disabled and the pin becomes a digital input pin RE3.
To disable the MCLR pin, make the MCLRE = OFF.

#pragma config MCLRE = OFF       // MCLR Disabled

#pragma config MCLRE = ON        // MCLR Enabled

Low Power Timer1 Oscillator Enable

The timer1 oscillator can operate in two power consumption modes, low power, and high power levels. The LPT1OSC configuration bit controls the power mode. The default configuration is high power mode.

#pragma config LPT1OSC = OFF       // Timer1 oscillator configured for high power

#pragma config LPT1OSC = ON        // Timer1 oscillator configured for low power

Port B A/D Enable

PIC18F4550 has 13 channels of analog to digital converter. The five channels reside on PortB<4:0> bits. In order to use it as A/D converter, we need to set the PBADEN bit as ON which will configure them as analog input on RESET.

#pragma config PBADEN = OFF       // PortB<4:0> pins are configured as digital I/O on Reset

#pragma config PBADEN = ON        // PortB<4:0> pins are configured as analog I/O on Reset

CCP2 Mux bit

The pin assignment for CCP2 can be changed based on the configuration bit CCP2MX. The default option is RC2 (CCP2MX = 1). If the bit is 0, CCP2 will be multiplexed with RB3.

#pragma config CCP2MX = OFF       // CCP2 input/output is multiplexed with RB3

#pragma config CCP2MX = ON       // CCP2 input/output is multiplexed with RC1

Stack Overflow Reset

PIC18F4550 can be configured to RESET on stack overflow conditions. In order to enable this option, STVREN bit should be enabled.

#pragma config STVREN = OFF       // Stack overflow reset

#pragma config STVREN = ON        // Stack overflow reset OFF

Low Voltage ICSP

The LVP bit is for enabling low voltage programming mode. The advantage of low voltage programming is that the device can be programmed with ordinary logic levels whereas in high voltage programming, the MCLR pin should be connected to the voltage level more than Vdd. In low voltage programming mode, it uses only single supply. To enter programming mode, PGM bit should be connected to Vdd, so the bit PGM (RB5) will not be available for I/O operation.

#pragma config LVP = OFF       // Low voltage programming mode OFF

#pragma config LVP = ON        // Low voltage programming mode ON

Dedicated In-Circuit Debug/Programming Enable

44-pin TQFP devices can use NC (No Connect) pins as dedicated In-Circuit Debug and In-Circuit Serial Programming pins. So the RB5, RB6, RB7 pins can be used for digital I/O operations. This feature is not available in 40-pin DIP devices. To use this feature, make ICPRT = ON.

#pragma config ICPRT = OFF       // Dedicated ICD/ICSP pins enabled

#pragma config ICPRT = OFF       // Dedicated ICD/ICSP pins disabled

Extended Instruction Set Enable

PIC18F4550 has 75 instructions by default, but there are 8 additional instructions to the core CPU functionality. To enable them, we need to set XINST configuration bit.

#pragma config XINST = OFF       // Extended instruction set disabled

#pragma config XINST = ON        // Extended instruction set enabled

Background Debugger Enable

Background Debug control interface allows you read/write access to RAM memory, SFRs, and emulation registers while your program is running or even sleeping. To enable the feature, set the configuration bit DEBUG.

#pragma config DEBUG = OFF       // Background debugger disabled

#pragma config DEBUG = ON        // Background debugger enabled

Code protection

The user program memory is divided into five blocks, one of which is boot block of 2Kbytes. Each of these blocks has three code protection bits associated with them. They are

Code protect bit (CPn)
Write protect bit (WRTn)
External Block Table Read bit (EBTRn)

Program Memory Code protection

CPn bits control the external reads and write, WRTn bits protect the block memory from table writes and EBTRn bit control table reads. Resetting the bit will activate the protection of, For example, to protect Block 0 from external reads and writes, set CP0 as 0. For XC8, put CP0 = ON

Data EEPROM Code protection

The data EEPROM is protected from external reads and writes by using two configuration bits, CPD and WRTD. CPD controls internal and external reads and writes whereas WRTD controls internal reads and writes.

#pragma config CPD = ON        // Data EEPROM Code protection ON

#pragma config WRTD = OFF      // Data EEPROM Write protection OFF

Configuration Register Protection

The WRTC configuration bit controls the protection of configuration register. It can be configured to write-protect the configuration register. WRTC bit can only be changed by ICSP or external programmers.

#pragma config WRTC = ON        // Configuration register protection ON

Further reading: We’ve prepared a complete guide on PIC Microcontrollers.