CCP module in PIC18F4550

///CCP module in PIC18F4550
  • CCP module in PIC18F4550

CCP module in PIC18F4550

Capture and compare features allow the user to time and control different events. PIC18F4550 has a built-in peripheral module called the CCP (Capture/Compare/PWM) module for this purpose. The CCP module in PIC18F4550 supports two independent instances of Capture, Compare and PWM feature. An in-depth description of generating PWM signal in PIC18F4550 can be found in our previous chapter Pulse Width Modulation Using PIC18F4550. Here we will learn about Capture and Compare features of the CCP module.

The Capture and Compare modes are configured with CCP1CON and CCP2CON registers. The occurrence of an event is notified by setting the respective CCPxIF flag bit. The Timer/Counter unit in Timer 1 or Timer 3 is used for its timing or counting functions and must also be configured properly. The complete configuration of Timers in PIC18F4550 can be found in our previous tutorial Timer and Counter with PIC18F4550. Here we will only be discussing the registers relevant to our cause.

Timer 1

Timer 1 is configured with T1CON register. The 16-bit timer value is stored in 8 bit TMR1H and TMR1L registers and can collectively be accessed as a single 16-bit register called TMR1.

T1con

T1CON_Capture and Compare in PIC18F4550

RD16:- Enable 16-bit operation of Timer 1
T1CKPS[1:0]:- Used to select the Prescale value of Timer 1 as 1, 2, 4 or 8
TMR1ON:- Enables Timer 1 operation

Timer 3

Timer 3 is configured with T3CON register. The 16-bit timer value is stored in 8 bit TMR3H and TMR3L registers and can collectively access as a single 16-bit register called TMR3.

T3CON

T3CON_Capture and Compare in PIC18F4550

RD16:- Enable 16-bit operation of Timer 3
T3CCP2, T3CCP1:- Used to select Timer 1 or Timer 3 as a source for CCP1 and CCP2 operation

  • 1x: Timer3 is the capture/compare clock source for both CCP modules
  • 01: Timer3 is the capture/compare clock source for CCP2 and Timer1 is the capture/compare clock source for CCP1
  • 00: Timer1 is the capture/compare clock source for both CCP modules

T1CKPS[1:0]:- Used to select the Prescale value of Timer 3 as 1, 2, 4 or 8
TMR1ON:- Enables Timer 3 operation

CCP Module in PIC18F4550

The both CCP module has an associated CCPxCON control register and CCPRx data register.

CCPxCON: CCP Control Register

CCPxCON_T1CON_Capture and Compare in PIC18F4550

CCxM[3:0]:- Used to specify the mode of operation of CCPx module

  • 0000 : Capture/Compare/PWM disabled (resets CCPx module)
  • 0010: Compare mode: Toggle output on match (CCPxIF bit is set)
  • 0100: Capture mode: Every falling edge
  • 0101: Capture mode: Every rising edge
  • 0110: Capture mode: Every 4th rising edge
  • 0111: Capture mode: Every 16th rising edge
  • 1000: Compare mode: Initialize CCPx pin low; on compare, match, force CCPx pin high
    (CCPxIF bit is set)
  • 1001: Compare mode: Initialize CCPx pin high; on compare match, force CCPx pin low
    (CCPxIF bit is set)
  • 1010: Compare mode: Generate software interrupt on compare match (CCPxIF bit is set,
    CCPx pin reflects I/O state)
  • 1011: Compare mode: Trigger special event, reset a timer, start A/D conversion on CCP2 match
    (CCPxIF bit is set)
  • 11xx: PWM mode

CCPRx

The 8 bit registers CCPRxH and CCPRxL together form the CCPRx data register. In Capture mode, the CCPRx register is loaded with the value captured from the TMR1 or TMR3 register in case of an event. In Compare mode the CCPRx register is used to store the value to be compared with the TMR1 or TMR3 register.

Capture Mode

The Capture Mode is used to time a particular event. When the event occurs the source timer value is loaded to the CCPRx data register. The value loaded in the CCPRx register will provide us the timing of the event or the time delay between two instances of the event. The event can be recognized as a rising edge or falling edge of the CCPx pin. Two alternate cases of 4th and 16th voltage rise can also be used. The event is specified with the help of the CCPxCON register.

To set the CCP module in Capture Mode we need to configure both the CCP and Timer Control registers. Timer 1 or Timer 3 can be chosen to source the CCP module. The timer selection is specified with the T3CCPx bits in the T3CON register. The CCP pin should also be configured as an input pin to read the event occurrence.

Here we will use the CCP 1 module in Capture Mode to detect every falling edge at RC2/CCP1 input pin, sourced with Timer 1 module.

Firmware Example

Following the proper capture mode configuration, whenever a falling edge event is applied on the CCP 1 pin the CCP1IF interrupt flag is set and the TMRx timer data is loaded to the CCPRx data register. The interrupt flag can be continuously polled or used to generate the interrupt to detect the event. Upon detecting an event, the value loaded to CCPRx data register can be used to get an estimate of the event timing. The CCP1IF interrupt flag must be software cleared after the occurrence of an event to detect the next event.

Compare Mode

The Compare Mode is used to control a particular event according to a required timing. The timing data to CCP module can be sourced with either Timer 1 or Timer 3 and the event trigger output is obtained at the CCPx pin.

The CCP module is set in Compare Mode by configuring the CCP and Timer control registers. The CCPRx data register is loaded with a value which is continuously compared with the TMRx timer data register. Whenever a compare match is obtained between the TMRx and CCPRx values, an event trigger is applied at the CCPx output pin. The nature of the required event trigger can be specified with the CCPxM bits in the CCPxCON control register.

Since the timer automatically resets after overflow, the event trigger is obtained periodically until the CCP or Timer module is disabled. The CCPxIF interrupt flag is also set at a compare match and must be software cleared.

Here we will configure the CCP 1 module, sourced by Timer 1, to provide a toggle output at CCP 1 pin for every compare match.

Firmware Example

The output obtained here would be a square wave with its time period linearly proportional to the value loaded to the CCPR1 data register. The nature of compare match output at CCP 1 pin can be customized with CCPxM bits in CCP1CON register and can be applied as a control signal to a peripheral device.

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