External Interrupt in 8051 microcontroller

///External Interrupt in 8051 microcontroller

External Interrupt in 8051 microcontroller

The interrupt mechanism is one of the most important features of a microcontroller. An interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention. As code size increases and your application handles multiple modules, sequential coding would be too long and too complex. The interrupt mechanism helps to embed your software with hardware in a much simpler and efficient manner. In this topic, we will discuss how to implement a basic interrupt mechanism.

Configuring AT89S8253 for External Interrupt

The AT89S8253 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt.
Each of these interrupts sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.

IE register (Interrupt Enable Register)

EA bit enables or disables all interrupt sources (globally):

  • 0 – disables all interrupts (even enabled).
  • 1 – enables specific interrupts.

ET0 bit enables or disables Timer T0 interrupt:

  • 0 – Timer T0 interrupt disabled.
  • 1 – Timera T0 interrupt enabled.

TCON

TCON register is also one of the registers whose bits are directly in control of timer operation. The 4 bits in LSB is used for interrupt control.

  • TF1 bit is automatically set when the Timer 1 overflow.
  • TR1 bit enables the Timer 1.
    • 1 – Timer 1 is enabled.
    • 0 – Timer 1 is disabled.
  • TF0 bit is automatically set when the Timer 0 overflow.
  • TR0 bit enables the timer 0.
    • 1 – Timer 0 is enabled.
    • 0 – Timer 0 is disabled.
  • IE1 – External Interrupt 1 edge detection flag.
    • This bit is set by the processor when there is an interrupt at INT1.
    • It is cleared by processor when there is a jump to Interrupt Service Routine (ISR), i.e. interrupt is processed.
  • IT1
    • 1 – interrupt triggered by falling edge.
    • 0 – interrupt triggered by a low level.
  • IE0 – External Interrupt 0 edge detection flag.
    • This bit is set by the processor when there is an interrupt at INT0.
    • It is cleared by the processor when there is a jump to Interrupt Service Routine (ISR), i.e. interrupt is processed.
  • IT0
    • 1 – interrupt triggered by falling edge.
    • 0 – interrupt triggered by a low level.

Firmware

  • Register configuration for External interrupt

  • Interrupt service routine

 

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