External Interrupt in PIC18F4550

///External Interrupt in PIC18F4550
  • External Interrupt in PIC18F4550

External Interrupt in PIC18F4550

An interrupt is a signal to the processor of the occurrence of an event by hardware or software. The processor may choose to accept or ignore this signal. The response of the processor to an interrupt is configured with the help of registers such as INTCON, PIR, PIE and IPR registers as specified in our previous chapter on Interrupt Handling in PIC18F4550.

An interrupt request is associated with a particular code sequence is called as an Interrupt Service Routine(ISR) or interrupt vector. Upon receiving a valid interrupt, the processor will halt current code execution, save next instruction address and status to stack, execute the ISR and then resume the previous code sequence execution after restoring data from the stack.

External Interrupt in PIC18F4550

An external interrupt happens due to an interference by some external hardware on specific pins of the microcontroller. PIC18F4550 can handle up to three external interrupts.

External Interrupt in PIC18F4550

Configuration bits for External Interrupt

To configure the processor to receive and process interrupt request we use the following registers associated with the external interrupt. We will focus only on bits relevant to an external interrupt.

RCON

External Interrupt in PIC18F4550

  • IPEN: Interrupt Priority Enable bit. Enables priority levels when set.

INTCON

External Interrupt in PIC18F4550

  • GIE/GIEH: Global Interrupt Enable bit
    • When IPEN is disabled, GIE enables all interrupts that sets
    • When IPEN is enabled, GIEH enables all high priority interrupts that sets
  • PEIE/GIEL: Peripheral Interrupt Enable bit
    • When IPEN is disabled, PEIE enables all peripheral interrupts that sets
    • When IPEN is enabled, GIEL enables all low priority interrupts
  • INT0IE: INT0 External Interrupt Enable bit. Enables the INT0 external interrupt that sets
  • INT0IF: INT0 External Interrupt Flag bit. Sets when INT0 external interrupt occur

INTCON3

External Interrupt in PIC18F4550

  • INTxIP: INTx External Interrupt Priority bit. INTx External Interrupt is set as a High priority interrupt
  • INTxIE: INTx External Interrupt Enable bit. Enables the INTx external interrupt when set
  • INTxIF: INTx External Interrupt Flag bit. Sets when INTx external interrupt occur

The response of the processor to an interrupt signal will depend on these enable, priority and flag bits.

To obtain a response to the interrupt we will use the 16*2 LCD connected to PORT A and PORT D as configured in our previous chapter on 16*2 Character LCD Interfacing with PIC Microcontroller in 8-bit Mode. We will also need the following functions to use the LCD

  • lcd_init() – To initialise the LCD in 8 bit mode
  • lcd_data(char) – To display a given character
  • lcd_cmd(int) – To execute an LCD command

Now, let’s configure the processor to receive all three external interrupts INT0, INT1, and INT2. The external interrupt pins are configured to input pins and use TRISB register to receive the interrupt request. We will be using priority mode and will configure INT1 as a high priority interrupt and INT2 as a low priority interrupt. So also enable the GIEH and GIEL bits.

Firmware Example:

INT0

Enable the INTo interrupt and clear the flag bit.

INT1

Enable the INT1 interrupt, set the priority bit to high and clear the flag bit

INT2

Enable the INT2 interrupt, set the priority bit to low and clear the flag bit

A code sequence to display a character at a particular rate is implemented with interrupt configuration.

Interrupt Service Routine

ISR(Interrupt Service Routine) defines both high priority and low priority interrupts.ISR of XC8 compiler as in this format

Here we will be defining the INT0 ISR to display the character ‘b’ three times with 200ms interval. To clear display use INT1 ISR. To display the character ‘c’ three times at a 200ms interval use INT2 ISR.

Polling inside the ISR with the help of flag bit detecting interrupt. At the end of the code sequence, the interrupt flag must be clear.

High priority interrupt

High priority interrupt vector occupies the position 008h in the program memory. They are defined with <type> parameter as high_priority.

Low priority interrupt

Low priority interrupt vector occupies the position 018h in the program memory. They are defined with <type> parameter as low_priority.

In this program, we can observe that any of the three interrupts can interrupt a normal code sequence execution. A  high priority interrupt can interrupt a low priority interrupt without the converse being true. The normal program execution will resume after the ISR execution.

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